Memory peripheral circuit having three-dimensional transistors and method for forming the same

US12063784B2 · kind B2 · utility

Assignee

• YANGTZE MEMORY TECHNOLOGIES CO., LTD. · CN

Inventors

• Liang Chen · 红钢城街道, CN
• Chao Sun · Hangzhou City, CN
• Wei Liu · 红钢城街道, CN
• Wenshan Xu · 红钢城街道, CN
• Wu Tian · 红钢城街道, CN
• Ning Jiang · 红钢城街道, CN
• Lei Xue · 红钢城街道, CN

Key dates

• Filing date: Sep 22, 2021
• Grant date: Aug 13, 2024
• Expiry date: Oct 7, 2042

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2924/14511
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

In certain aspects, a memory device includes an array of memory cells, a plurality of word lines coupled to the array of memory cells, and a plurality of peripheral circuits coupled to the array of memory cells and configured to control the array of memory cells. A first peripheral circuit of the plurality of peripheral circuits includes a first three-dimensional (3D) transistor coupled to the array of memory cells through at least one of the plurality of word lines. The first 3D transistor includes a 3D semiconductor body, and a gate structure in contact with a plurality of sides of the 3D semiconductor body. The gate structure includes a gate dielectric and a gate electrode.