Compute-in-memory device and method
US12063786B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 21, 2022 |
| Grant date | Aug 13, 2024 |
| Priority date | — |
| Expiry date | Apr 21, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/54
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In some embodiments, an integrated circuit (IC) device includes an active semiconductor layer, a circuitry formed within the active semiconductor layer, a region including conductive layers formed above the active semiconductor layer, and a memory module formed in the region. The memory device includes a three-dimensional array of memory cells, each adapted to store a weight value, and adapted to generate at each memory cell a signal indicative of a product between the stored weight value and an input signal applied to the memory cell. The memory module is further adapted to transmit the product signals from the memory cell simultaneously in the direction of the active semiconductor layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.