Multi-port circuit architecture
US12066855B2 · kind B2 · utility
0Cited by
2References
20Claims
0Family size
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Key dates
| Filing date | Dec 30, 2022 |
| Grant date | Aug 20, 2024 |
| Priority date | — |
| Expiry date | Dec 31, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/3062
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Various implementations described herein are related to a device having multi-port circuit architecture with multiple ports. The multi-port circuit architecture may expand a primary clock into multiple dummy clocks so as to separately track, simulate and report clock power consumption for each port of the multiple ports to a central processing unit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.