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US12066949B2 · kind B2 · utility
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4References
11Claims
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Key dates
| Filing date | Dec 3, 2021 |
| Grant date | Aug 20, 2024 |
| Priority date | — |
| Expiry date | Dec 3, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/7201
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Translated addresses of a memory device can be stored in a first LUT maintained by control circuitry. Untranslated addresses can be stored in a second LUT maintained by the control circuitry. In response to a translation request for a particular translated address of the memory device corresponding to a target untranslated address, an index of the second LUT associated with the target untranslated address can be determined, the index of the second LUT can be mapped to an index of the first LUT, and the particular translated address corresponding to the target untranslated address can be retrieved from the first LUT.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.