Defect resistant designs for location-sensitive neural network processor arrays

US12067472B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Rathinakumar Appuswamy · San Jose, US
• John V. Arthur · Mountain View, US
• Andrew S. Cassidy · San Jose, US
• Pallab Datta · San Jose, US
• Steven K. Esser · San Jose, US
• Myron D. Flickner · San Jose, US
• Jennifer Klamo · San Jose, US
• Dharmendra S. Modha · San Jose, US
• Hartmut Penner · San Jose, US
• Jun Sawada · Austin, US
• Brian Taba · Cupertino, US

Key dates

• Filing date: Mar 30, 2018
• Grant date: Aug 20, 2024
• Expiry date: Mar 16, 2041

Classification

• Technology area (CPC G): Physics
• CPC primary: G06N3/048
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

Defect resistant designs for location-sensitive neural network processor arrays are provided. In various embodiments, plurality of neural network processor cores are arrayed in a grid. The grid has a plurality of rows and a plurality of columns. A network interconnects at least those of the plurality of neural network processor cores that are adjacent within the grid. The network is adapted to bypass a defective core of the plurality of neural network processor cores by providing a connection between two non-adjacent rows or columns of the grid, and transparently routing messages between the two non-adjacent rows or columns, past the defective core.