Two-pass corrective programming for memory cells that store multiple bits and power loss management for two-pass corrective programming
US12068034B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 30, 2022 |
| Grant date | Aug 20, 2024 |
| Priority date | — |
| Expiry date | Mar 3, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/0483
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Exemplary methods, apparatuses, and systems including a programming manager for controlling writing data bits to a memory device. The programming manager receives a first set of data bits for programming to memory. The programming manager writes a first subset of data bits to a first wordline during a first pass of programming. The programming manager writes a second subset of data bits of the first set of data bits to a buffer. The programming manager receives a second set of data bits for programming. The programming manager writes the second subset of data bits of the first set of data bits to the first wordline during a second pass of programming to increase a bit density of memory cells in the first wordline in response to receiving the second set of data bits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.