Magnetic random access memory structure
US12069960B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 15, 2021 |
| Grant date | Aug 20, 2024 |
| Priority date | — |
| Expiry date | Jun 14, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N50/80
Abstract
The invention provides a semiconductor structure, the semiconductor structure includes a dielectric layer, a plurality of MTJ stacked elements and at least one dummy MTJ stacked element located in the dielectric layer, a first nitride layer covering at least the sidewalls of the MTJ stacked elements and the dummy MTJ stacked elements, a second nitride layer covering the top surfaces of the dummy MTJ stacked elements, the thickness of the second nitride layer is greater than the thickness of the first nitride layer, and a plurality of contact structures located in the dielectric layer and electrically connected with each MTJ stacked element.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.