Three dimensional perpendicular magnetic tunnel junction with thin film transistor array
US12069964B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 9, 2022 |
| Grant date | Aug 20, 2024 |
| Priority date | — |
| Expiry date | Aug 23, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N50/85
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for manufacturing a magnetic random access memory array incudes forming a source region within a surface of a substrate, forming an array of three-dimensional (3D) structures over the substrate, each 3D structure being separated from an adjacent 3D structure by a cavity region, depositing a channel material on a surface of at least one sidewall of each 3D structure, depositing a gate dielectric material over the channel material on the surface of the at least one sidewall of each 3D structure, forming a first isolation region in each cavity region between adjacent 3D structures over the substrate, and forming a first gate region over the first isolation region in each cavity region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.