Highly integrated scalable, flexible DSP megamodule architecture
US12072812B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 22, 2021 |
| Grant date | Aug 27, 2024 |
| Priority date | — |
| Expiry date | Apr 22, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03H2017/0298
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed embodiments include an electronic device having a processor core, a memory, a register, and a data load unit to receive a plurality of data elements stored in the memory in response to an instruction. All of the data elements hare the same data size, which is specified by one or more coding bits. The data load unit includes an address generator to generate addresses corresponding to locations in the memory at which the data elements are located, and a formatting unit to format the data elements. The register is configured to store the formatted data elements, and the processor core is configured to receive the formatted data elements from the register.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.