Memory device deserializer circuit with a reduced form factor
US12073918B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 17, 2023 |
| Grant date | Aug 27, 2024 |
| Priority date | — |
| Expiry date | Feb 17, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/0483
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory sub-system including a memory device, wherein the memory device includes a circuit, operatively coupled to an array data bus of a memory array, and control logic, operatively coupled with the circuit, to perform operations including: deserializing a serial data stream in a first time domain to generate at least one of a set of rising data portions or a set of falling data portions; and synchronizing the at least one of the set of rising data portions or the set of falling data portions in a second time domain using at least one of a set of rising edge clock signals or a set of falling edge clock signals generated by a ring counter portion.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.