Semiconductor package
US12074141B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 19, 2021 |
| Grant date | Aug 27, 2024 |
| Priority date | — |
| Expiry date | May 24, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2225/06586
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
There is provided a semiconductor device comprising a first semiconductor chip which includes a first chip substrate, and a first through via penetrating the first chip substrate, a second semiconductor chip disposed on the first semiconductor chip, and includes a second chip substrate, and a second through via penetrating the second chip substrate, and a connecting terminal disposed between the first semiconductor chip and the second semiconductor chip to electrically connect the first through via and the second through via. The semiconductor device further comprising an inter-chip molding material which includes a filling portion that fills between the first semiconductor chip and the second semiconductor chip and encloses the connecting terminal, an extension portion that extends along at least a part of a side surface of the second semiconductor chip, and a protruding portion protruding from the extension portion.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.