Three-dimensional memory device and method for forming the same
US12075621B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 27, 2021 |
| Grant date | Aug 27, 2024 |
| Priority date | — |
| Expiry date | Dec 17, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/50
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A three-dimensional (3D) memory device includes a doped semiconductor layer, a stack structure, and a channel structure. The stack structure includes interleaved conductive layers and dielectric layers formed on the doped semiconductor layer. The conductive layers include a plurality of word lines, and a drain select gate line. The channel structure extends through the stack structure along a first direction and is in contact with the doped semiconductor layer. The channel structure includes a semiconductor channel, and a memory film over the semiconductor channel. The drain select gate line is in direct contact with the semiconductor channel, each of the plurality of word lines is in direct contact with the memory film, and the drain select gate line and the plurality of word lines include a same material.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.