Distribution of data and memory timing parameters across memory modules based on memory access patterns
US12079145B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 30, 2023 |
| Grant date | Sep 3, 2024 |
| Priority date | — |
| Expiry date | Jan 30, 2043 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor distributes memory timing parameters and data among different memory modules based upon memory access patterns. The memory access patterns indicate different types, or classes, of data for an executing workload, with each class associated with different memory access characteristics, such as different row buffer hit rate levels, different frequencies of access, different criticalities, and the like. The processor assigns each memory module to a data class and sets the memory timing parameters for each memory module according to the module's assigned data class, thereby tailoring the memory timing parameters for efficient access of the corresponding data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.