Semiconductor structure and method of wafer bonding
US12080622B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 18, 2023 |
| Grant date | Sep 3, 2024 |
| Priority date | — |
| Expiry date | Apr 18, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L23/3736
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor structure includes a glass substrate and a device structure. The glass substrate includes a glass layer, a heat dissipation layer and a silicon nitride layer stacked from bottom to top. The device structure includes at least one semiconductor device integrated in a device layer situated over the silicon nitride layer of the glass substrate. Or, the glass substrate includes a glass layer and a silicon nitride layer stacked from bottom to top. The device structure includes at least one semiconductor device integrated in a device layer, and a heat dissipation layer is stacked on the device layer, wherein the heat dissipation layer is bonded with the silicon nitride layer of the glass substrate. The present invention also provides a method of wafer bonding for manufacturing said semiconductor structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.