Three-dimensional memory device and method for forming the same
US12082407B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 23, 2021 |
| Grant date | Sep 3, 2024 |
| Priority date | — |
| Expiry date | Nov 6, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D88/00
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A three-dimensional (3D) memory device includes a first substrate, a first semiconductor structure, and a second semiconductor structure. The first semiconductor structure is disposed on the first substrate. The first semiconductor structure includes a second substrate, and a peripheral device disposed over the second substrate, and the peripheral device is formed facing the first substrate. The second semiconductor structure is disposed on the first semiconductor structure. The second semiconductor structure includes a doped semiconductor layer, and a memory array structure disposed between the doped semiconductor layer and the first semiconductor structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.