Patent · US Active

Three-dimensional memory devices having first semiconductor structure bonded with second semiconductor structure each including peripheral circuit and methods for forming the same

US12082408B2 · kind B2 · utility

0Cited by

1References

20Claims

0Family size

Assignee

YANGTZE MEMORY TECHNOLOGIES CO., LTD. · CN

Inventors

Yuancheng Yang · Hubei, CN
Wenxi Zhou · 红钢城街道, CN
Zhiliang Xia · 红钢城街道, CN
Wei Liu · 红钢城街道, CN

Key dates

Filing date	Sep 22, 2021
Grant date	Sep 3, 2024
Priority date	—
Expiry date	Oct 20, 2042

Classification

Technology area (CPC H)Electricity
CPC primaryH10D88/00
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

In certain aspects, a three-dimensional (3D) memory device includes a first semiconductor structure, a second semiconductor structure, and a bonding interface between the first and second semiconductor structures. The first semiconductor structure includes an array of NAND memory strings, a first peripheral circuit of the array of NAND memory strings including a first transistor, a polysilicon layer between the array of NAND memory strings and the first peripheral circuit, and a first semiconductor layer in contact with the first transistor. The polysilicon layer is in contact with sources of the array of NAND memory strings. The second semiconductor structure includes a second peripheral circuit of the array of NAND memory strings including a second transistor, and a second semiconductor layer in contact with the second transistor. The second peripheral circuit is between the bonding interface and the second semiconductor layer. The first semiconductor layer is between the polysilicon layer and the second semiconductor layer.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.