High throughput parallel architecture for recursive sinusoid synthesizer
US12086568B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 14, 2023 |
| Grant date | Sep 10, 2024 |
| Priority date | — |
| Expiry date | Apr 14, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2005/00078
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A first multiplier multiplies a first input with a first coefficient and a first adder sums an output of the first multiplier and a second input to generate a first output. A second multiplier multiplies a third input with a second coefficient, a third multiplier multiplies a fourth input with a third coefficient, and a second adder sums outputs of the second and third multipliers to generate a second output. The second and third inputs are derived from the first output and the first and fourth inputs are derived from the second output. The first and second outputs generate digital values for first and second digital sinusoids, respectively.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.