High aspect ratio via fill process employing selective metal deposition and structures formed by the same
US12087626B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 25, 2021 |
| Grant date | Sep 10, 2024 |
| Priority date | — |
| Expiry date | Jan 27, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/50
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method includes forming a semiconductor device, forming a combination of a connection-level dielectric layer and a connection-level metal interconnect structure over the semiconductor device, forming a line-and-via-level dielectric layer over the connection-level dielectric layer, forming an integrated line-and-via cavity through the line-and-via-level dielectric layer over the connection-level metal interconnect structure, selectively growing a conductive via structure consisting essentially of an elemental metal that is not copper from a physically exposed conductive surface located at a bottom of the via portion of the integrated line-and-via cavity without filling a line portion of the integrated line-and-via cavity, and forming a copper-based conductive line structure that includes copper at an atomic percentage that is greater than 90% in the line portion of the integrated line-and-via cavity.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.