Patent · US Active

Clock gating using a cascaded clock gating control signal

US12088296B2 · kind B2 · utility

0Cited by

5References

20Claims

0Family size

Assignee

Advanced Micro Devices, Inc. · US

Inventors

Ramon Mangaser · Boxborough, US
Srikanth Reddy Gruddanti · Kanchinakote, IN
Prasant Kumar Vallur · Hyderabad, IN
Krishna Reddy Mudimela Venkata · Bengaluru, IN
Oikwan Tsang · San Jose, US

Key dates

Filing date	Dec 17, 2021
Grant date	Sep 10, 2024
Priority date	—
Expiry date	Dec 17, 2041

Classification

Technology area (CPC H)Electricity
CPC primaryH03K3/037
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A clock circuit for clock gating using a cascaded clock gating control signal, including: a first B-latch accepting, as input, a clock gating control signal and enabled by a first clock signal; a second B-latch accepting, as input, an output from the first B-latch and enabled by a second clock signal; and a first logic outputting, based on the first B-latch, a first gated clock signal; and a second logic outputting, based on the second B-latch, a second gated clock signal.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.