Hierarchical power management apparatus and method
US12093100B2 · kind B2 · utility
Assignee
Inventors
- Vivek Garg
- Ankush Varma
- Krishnakanth V. Sistla
- Nikhil Gupta
- Nikethan Shivanand Baligar
- Stephen Wang
- Nilanjan PALIT
- Timothy Y. Kam
- Adwait Purandare
- Ujjwal Gupta
- Stanley Chen
- Dorit Shapira
- Shruthi VENUGOPAL
- Suresh Chemudupati
- Rupal Parikh
- Eric J. Dehaemer
- Pavithra Sampath
- Phani Kumar Kandula
- Yogesh Bansal
- Dean Mulla
- Michael Tulanowski
- Stephen Paul Haake
- Andrew J. Herdrich
- Ripan Das
- Nazar Haider
- Aman Sewani
Key dates
| Filing date | Sep 26, 2020 |
| Grant date | Sep 17, 2024 |
| Priority date | — |
| Expiry date | Oct 17, 2042 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Hierarchical Power Management (HPM) architecture considers the limits of scaling on a power management controller, the autonomy at each die, and provides a unified view of the package to a platform. At a simplest level, HPM architecture has a supervisor and one or more supervisee power management units (PMUs) that communicate via at least two different communication fabrics. Each PMU can behave as a supervisor for a number of supervisee PMUs in a particular domain. HPM addresses these needs for products that comprise a collection of dice with varying levels of power and thermal management capabilities and needs. HPM serves as a unified mechanism than can span collection of dice of varying capability and function, which together form a traditional system-on-chip (SoC). HPM provides a basis for managing power and thermals across a diverse set of dice.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.