High throughput digital filter architecture for processing unary coded data
US12093193B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 12, 2020 |
| Grant date | Sep 17, 2024 |
| Priority date | — |
| Expiry date | Feb 3, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F17/16
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Individual bits of a K bit unary data word, wherein K is greater than one, are applied to K polyphase finite impulse response filter circuits. Each polyphase finite impulse response filter circuit receives a different bit and operates with a single bit precision to generate from each received bit a filtered output data word. A gain adjustment is applied by a gain stage circuit to each filtered output data word to generate a corresponding gain adjusted output data word. The gain adjusted output data words from the gain stage circuits are summed to generate an output data word. The unary data word may be output from a source such as a data encoder or a quantizer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.