Dual silicide process using ruthenium silicide
US12094785B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 15, 2021 |
| Grant date | Sep 17, 2024 |
| Priority date | — |
| Expiry date | Jul 22, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/0174
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Methods for forming a semiconductor structure and semiconductor structures are described. The method comprises patterning a substrate to form a first opening and a second opening, the substrate comprising an n transistor and a p transistor, the first opening over the n transistor and the second opening over the p transistor. The substrate may be pre-cleaned. A ruthenium silicide (RuSi) layer is selectively deposited on the p transistor. A titanium silicide (TiSi) layer is formed on the n transistor and the p transistor. An optional barrier layer may be formed on the titanium silicide (TiSi) layer. The method may be performed in a processing chamber without breaking vacuum.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.