Characterizing defects in semiconductor layers
US12094787B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 3, 2021 |
| Grant date | Sep 17, 2024 |
| Priority date | — |
| Expiry date | Apr 19, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/875
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of characterizing defects in semiconductor layers may include forming a first electrode, a first barrier layer, a semiconductor layer, and a second electrode, where the first barrier layer is between the first electrode and the semiconductor layer, and the semiconductor layer is between the first barrier layer and the second electrode. The method may also include causing current to flow through the semiconductor layer, where the first barrier layer prevents the current from entering a conduction band of the semiconductor layer and instead causes current to flow through defects in the semiconductor layer. The method may also include characterizing the defects in the semiconductor layer based on the current flowing through the defects in the semiconductor layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.