Gate all around device
US12094946B2 · kind B2 · utility
0Cited by
11References
20Claims
0Family size
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Key dates
| Filing date | Apr 11, 2022 |
| Grant date | Sep 17, 2024 |
| Priority date | — |
| Expiry date | Nov 12, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/122
Abstract
A device includes a nanostructure, a gate dielectric layer, a gate electrode, and a gate contact. The nanostructure is over a substrate. The gate dielectric layer laterally surrounds the nanostructure. The gate electrode laterally surrounds the gate dielectric layer. The gate electrode has a bottom surface and a top surface both higher than a bottom end of the nanostructure. The gate electrode has a horizontal dimension decreasing from the bottom surface to the top surface. The gate contact is electrically coupled to the gate electrode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.