Error processing circuit, memory and operation method of the memory
US12099411B2 · kind B2 · utility
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19Claims
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Key dates
| Filing date | Feb 16, 2023 |
| Grant date | Sep 24, 2024 |
| Priority date | — |
| Expiry date | Feb 16, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/0411
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An error processing circuit includes: a first H matrix calculation circuit configured to calculate a first H matrix and upstream data to generate a partial first parity, during an encoding operation; a second H matrix calculation circuit configured to calculate a second H matrix and the upstream data to generate a second parity, during the encoding operation; and a parity calculation circuit configured to sum the partial first parity and the second parity to generate a first parity, during the encoding operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.