Controller for managing multiple types of memory
US12099457B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 16, 2022 |
| Grant date | Sep 24, 2024 |
| Priority date | — |
| Expiry date | Sep 23, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/1694
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems, apparatuses, and methods related to a controller for managing multiple types of memory are described. A controller includes a front end portion, a central controller portion, a back end portion, and a management unit can manage a first type of memory device that operates according to a first set of timing characteristics and a second type of memory device that operates according to a second set of timing characteristics. The central controller portion is configured to cause performance of a memory operation and comprises a cache memory to buffer data associated performance of the memory operation, a security component configured to encrypt the data before storing the data in the first type of memory device or the second type of memory device, and error correction code (ECC) circuitry to ECC encode and ECC decode the data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.