Memory device and erasing and verification method thereof
US12100456B2 · kind B2 · utility
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17References
20Claims
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Key dates
| Filing date | Apr 28, 2023 |
| Grant date | Sep 24, 2024 |
| Priority date | — |
| Expiry date | Apr 28, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/5621
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device includes a memory string and a control circuit coupled to the memory string. The memory string includes a top select gate, word lines, and a bottom select gate. The control circuit is configured to, in an erasing operation, apply an erasing voltage to the memory string, apply a verifying voltage to at least one word line of the word lines after applying the erasing voltage to the memory string, and apply a first turn-on voltage to the bottom select gate, before applying the verifying voltage to the at least one word line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.