Systems and methods for testing redundant fuse latches in a memory device
US12100467B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 24, 2022 |
| Grant date | Sep 24, 2024 |
| Priority date | — |
| Expiry date | Feb 10, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/1802
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An electronic device includes multiple memory elements including multiple redundant memory elements. The electronic device also includes repair circuitry configured to remap data to the multiple memory elements when a failure occurs. The repair circuitry includes multiple fuse latches configured to implement the remapping. The repair circuitry also includes latch testing circuitry configured to test functionality of the multiple fuse latches. The latch testing circuitry includes selection circuitry configured to enable selection of a first set of fuse latches of the multiple fuse latches for a test separate from a second set of fuse latches of the multiple fuse latches that are unselected by the selection circuitry.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.