Test mode security circuit
US12100476B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 12, 2022 |
| Grant date | Sep 24, 2024 |
| Priority date | — |
| Expiry date | Mar 25, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/46
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus includes a TM control circuit that is configured to receive address information corresponding to a TM function and compare the address information with an authorized TM list stored in a memory of the apparatus to determine if there is a match. If there is a match, a latch load signal pulse is output. A TM latch circuit programs one or more latches based on the address information and based on the latch load signal pulse. The TM latch circuit decodes information in the one or more latches and, based on the decoded information, outputs a test mode signal to turn on test mode operations in circuits associated with the TM function. The apparatus includes a plurality of TM functions for testing various features of the apparatus and the authorized TM list identifies which of the plurality of TM functions has been authorized for customer use.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.