Noise mitigation in single-ended links
US12101135B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 7, 2023 |
| Grant date | Sep 24, 2024 |
| Priority date | — |
| Expiry date | Sep 7, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L25/0264
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
An integrated circuit includes a first terminal for receiving a data signal, a second terminal for receiving an external reference voltage, a receiver, and a reference voltage generation circuit. The receiver is powered by a power supply voltage with respect to ground and has a first input coupled to the first terminal, a second input for receiving a shared reference voltage, and an output for providing a data input signal. The reference voltage generation circuit is coupled to the second terminal and receives the power supply voltage. The reference voltage generation circuit is operable to form the shared reference voltage by mixing noise from the power supply voltage and noise from the second terminal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.