Targets for diffraction-based overlay error metrology
US12105414B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 6, 2022 |
| Grant date | Oct 1, 2024 |
| Priority date | — |
| Expiry date | Dec 31, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L22/12
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
A method for semiconductor metrology includes depositing first and second overlying film layers on a semiconductor substrate and patterning the layers to define an overlay target. The target includes a first grating pattern in the first layer, including at least a first linear grating oriented in a first direction and at least a second linear grating oriented in a second direction perpendicular to the first direction, and a second grating pattern in the second layer, including at least a third linear grating identical to the first linear grating and a fourth linear grating identical to the second linear grating. The second grating pattern has a nominal offset relative to the first grating pattern by first and second displacements in the first and second directions, respectively. A scatterometric image of the substrate is captured and processed to estimate an overlay error between the patterning of the first and second layers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.