NAND string read voltage adjustment
US12105963B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 8, 2022 |
| Grant date | Oct 1, 2024 |
| Priority date | — |
| Expiry date | Feb 8, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/0483
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus includes a control circuit configured to connect to NAND strings that are connected to bit lines, where each bit line is connected to a plurality of NAND strings in a corresponding plurality of regions of a block. The control circuit is configured to apply a read voltage in read operations directed to NAND strings of the plurality of regions of the block and subsequently adjust the read voltage by a first predetermined amount for read operations directed to NAND strings of a first region of the block. The control circuit is further configured to adjust the read voltage by a second predetermined amount for read operations directed to NAND strings of a second region of the block. The first and second predetermined amounts are based on respective locations of the first and second regions in the block.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.