Systems, methods, and apparatuses for matrix operations
US12106100B2 · kind B2 · utility
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98References
19Claims
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Key dates
| Filing date | Jul 1, 2017 |
| Grant date | Oct 1, 2024 |
| Priority date | — |
| Expiry date | Jan 30, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/454
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Embodiments detailed herein relate to matrix (tile) operations. For example, decode circuitry to decode an instruction having fields for an opcode and a memory address; and execution circuitry to execute the decoded instruction to set a tile configuration for the processor to utilize tiles in matrix operations based on a description retrieved from the memory address, wherein a tile a set of 2-dimensional registers are discussed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.