Silent cache line eviction
US12111770B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 30, 2022 |
| Grant date | Oct 8, 2024 |
| Priority date | — |
| Expiry date | Oct 21, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/7209
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
System and techniques for silent cache line eviction are described herein. A memory device receives a memory operation from a host. The memory operation establishes data and metadata in a cache line of the memory device upon receipt. The metadata is stored in a memory element that corresponds to the cache line. Later, an eviction trigger to evict the cache line is identified. Then, in response to the eviction trigger, current metadata of the cache line is compared with the metadata in the memory element to determine whether the metadata has changed. the cache line can be evicted without writing to backing memory in response to the metadata being unchanged.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.