Out-of-order bit-flipping decoders for non-volatile memory devices
US12112041B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 22, 2022 |
| Grant date | Oct 8, 2024 |
| Priority date | — |
| Expiry date | Dec 15, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/09
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Devices, systems, and methods for reducing a latency of a decoder in a non-volatile memory are described. An example method includes receiving a noisy codeword that is based on a transmitted codeword generated from a low-density parity-check (LDPC) code, the LDPC code having an associated parity matrix comprising a plurality of columns of circulant matrices, performing a sorting operation that sorts the plurality of columns of circulant matrices in a descending order of a first quality metric to generate a plurality of sorted columns of circulant matrices, the first quality metric indicative of a number of errors in a corresponding column of circulant matrices, and iteratively processing the plurality of sorted columns of circulant matrices to determine a candidate version of the transmitted codeword.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.