Formation of metal vias on metal lines
US12113020B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 24, 2021 |
| Grant date | Oct 8, 2024 |
| Priority date | — |
| Expiry date | Feb 24, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/28562
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Exemplary semiconductor processing methods include forming a via in a semiconductor structure. The via may be defined in part by a bottom surface and a sidewall surface formed in the semiconductor structure around the via. The methods may also include depositing a tantalum nitride (TaN) layer on the bottom surface of the via. In embodiments, the TaN layer may be deposited at a temperature less than or about 200° C. The methods may still further include depositing a titanium nitride (TiN) layer on the TaN layer. In embodiments, the TiN layer may be deposited at a temperature greater than or about 300° C. The methods may additionally include depositing a fill-metal on the TiN layer in the via. In embodiments, the metal may be deposited at a temperature greater than or about 300° C.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.