Transistor and methods of forming integrated circuitry
US12113130B2 · kind B2 · utility
0Cited by
8References
20Claims
0Family size
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Key dates
| Filing date | May 10, 2023 |
| Grant date | Oct 8, 2024 |
| Priority date | — |
| Expiry date | May 10, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/0229
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A transistor comprises a top source/drain region, a bottom source/drain region, a channel region vertically between the top and bottom source/drain regions, and a gate operatively laterally-adjacent the channel region. At least one of the top source/drain region, the bottom source/drain region, and the channel region are crystalline. All crystal grains within the at least one of the top source/drain region, the bottom source/drain region, and the channel region have average crystal sizes within 0.064 μm3 of one another. Other embodiments, including methods, are disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.