Stochastic optimization of surface cacheability in parallel processing units
US12117939B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 21, 2021 |
| Grant date | Oct 15, 2024 |
| Priority date | — |
| Expiry date | Dec 21, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/6042
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processing system selectively allocates storage at a local cache of a parallel processing unit for cache lines of a repeating pattern of data that exceeds the storage capacity of the cache. The processing system identifies repeating patterns of data having cache lines that have a reuse distance that exceeds the storage capacity of the cache. A cache controller allocates storage for only a subset of cache lines of the repeating pattern of data at the cache and excludes the remainder of cache lines of the repeating pattern of data from the cache. By restricting the cache to store only a subset of cache lines of the repeating pattern of data, the cache controller increases the hit rate at the cache for the subset of cache lines.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.