Approximate data bus inversion technique for latency sensitive applications
US12117960B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 23, 2020 |
| Grant date | Oct 15, 2024 |
| Priority date | — |
| Expiry date | Jan 14, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/423
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems, methods, and apparatuses associated with an approximate majority based data bus inversion technique are disclosed. A method comprises obtaining, at a first device connected by a plurality of lanes to a second device, original data comprising first bits and second bits, where the first bits are to be transmitted in a new clock cycle via first lanes of the plurality of lanes, and the second bits are to be transmitted in the new clock cycle via second lanes of the plurality of lanes. The method further includes determining whether a first criterion associated with the first bits is met, determining whether a second criterion associated with the second bits is met, and transmitting an inverted version of the original data via the plurality of lanes based, at least in part, on determining that the first criterion and the second criterion are met.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.