Low resistance approaches for fabricating contacts and the resulting structures

US12119387B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Gilbert Dewey · Beaverton, US
• Nazila Haratipour · Hillsboro, US
• Siddharth Chouksey · Portland, US
• Jack T. Kavalieros · Portland, US
• Jitendra Kumar Jha · Hillsboro, US
• Matthew V. Metz · Portland, US
• Mengcheng Lu · Portland, US
• Anand S. Murthy · Beaverton, US
• Koustav Ganguly · Beaverton, US
• Ryan Keech · Portland, US
• Glenn A. Glass · Portland, US
• Arnab Sen Gupta · Beaverton, US

Key dates

• Filing date: Sep 25, 2020
• Grant date: Oct 15, 2024
• Expiry date: Feb 13, 2043

Classification

• Technology area (CPC B): Performing Operations; Transporting
• CPC primary: B82Y10/00
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

Low resistance approaches for fabricating contacts, and semiconductor structures having low resistance metal contacts, are described. In an example, an integrated circuit structure includes a semiconductor structure above a substrate. A gate electrode is over the semiconductor structure, the gate electrode defining a channel region in the semiconductor structure. A first semiconductor source or drain structure is at a first end of the channel region at a first side of the gate electrode. A second semiconductor source or drain structure is at a second end of the channel region at a second side of the gate electrode, the second end opposite the first end. A source or drain contact is directly on the first or second semiconductor source or drain structure, the source or drain contact including a barrier layer and an inner conductive structure.