Gate all around structure with additional silicon layer and method for forming the same
US12119404B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 29, 2023 |
| Grant date | Oct 15, 2024 |
| Priority date | — |
| Expiry date | Jun 29, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/0133
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Methods for manufacturing a semiconductor structure are provided. The method includes alternately stacking first semiconductor material layers and second semiconductor layers over a substrate and patterning the first semiconductor material layers and the second semiconductor layers to form a first fin structure and a second fin structure. The method also includes forming an insulating layer around the first fin structure and the second fin structure and forming a dielectric fin structure over the insulating layer and spaced apart from the first fin structure and the second fin structure. The method also includes forming a first source/drain structure attached to the first fin structure and forming a semiconductor layer covering the first source/drain structure. The method also includes oxidizing the semiconductor layer to form an oxide layer and forming a second source/drain structure attached to the second fin structure after the oxide layer is formed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.