Semiconductor integrated circuit device suppressing leakage current of multilayer wiring structures
US12125785B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 18, 2021 |
| Grant date | Oct 22, 2024 |
| Priority date | — |
| Expiry date | Jan 13, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L23/53257
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor integrated circuit device includes a substrate; a transistor on the substrate; an interlayer insulating film on the transistor; an insulating liner on the interlayer insulating film; a first insulating film on the insulating liner; and a first wiring layer on the interlayer insulating film and surrounded by the insulating liner. A height of a top surface of the first insulating film in a vertical direction from a main surface of the interlayer insulating film is different than a height of a top surface of the first wiring layer in the vertical direction. A step exists between the top surfaces of the first wiring layer and the first insulating film. A height of the first insulating film is greater than a height of the first wiring layer. A width of the first wiring layer gradually narrows as the first wiring layer extends upwards along the vertical direction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.