Carrying substrate, electronic package having the carrying substrate, and methods for manufacturing the same
US12125828B2 · kind B2 · utility
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1References
12Claims
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Assignee
Inventors
Key dates
| Filing date | Sep 11, 2023 |
| Grant date | Oct 22, 2024 |
| Priority date | — |
| Expiry date | Sep 11, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/16251
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of manufacturing a carrying substrate is provided. At least one circuit component is disposed on a first circuit structure. An encapsulation layer is formed on the first circuit structure and encapsulates the circuit component. A second circuit structure is formed on the encapsulation layer and electrically connected to the circuit component. The circuit component is embedded in the encapsulation layer via an existing packaging process. Therefore, the routing area is increased, and a package substrate requiring a large size has a high yield and low manufacturing cost.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.