Method and system for fabrication of a vertical fin-based field effect transistor

US12125914B2 · kind B2 · utility

Assignee

• SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC · US

Inventors

• Clifford Drowley · Santa Clara, US
• Ray Milano · Santa Clara, US
• Subhash Srinivas Pidaparthi · Santa Clara, US
• Andrew P. Edwards · San Jose, US
• Hao Cui · Gresham, US
• Shahin Sharifzadeh · Menlo Park, US

Key dates

• Filing date: Jun 23, 2023
• Grant date: Oct 22, 2024
• Expiry date: Jun 23, 2043

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/64

Abstract

A method of fabricating a vertical fin-based field effect transistor (FET) includes providing a semiconductor substrate having a first surface and a second surface, the semiconductor substrate having a first conductivity type, epitaxially growing a first semiconductor layer on the first surface of the semiconductor substrate, the first semiconductor layer having the first conductivity type and including a drift layer and a graded doping layer on the drift layer, and epitaxially growing a second semiconductor layer having the first conductivity type on the graded doping layer. The method also includes forming a metal compound layer on the second semiconductor layer, forming a patterned hard mask layer on the metal compound layer, and etching the metal compound layer and the second semiconductor layer using the patterned hard mask layer as a mask exposing a surface of the graded doping layer to form a plurality of fins surrounded by a trench.