Memory device and method for forming the same
US12127397B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 2, 2021 |
| Grant date | Oct 22, 2024 |
| Priority date | — |
| Expiry date | Jul 10, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/315
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present disclosure provides a forming method of a memory and a memory. The method includes: providing a substrate, wherein the substrate includes at least word line structures and active areas, and a bottom dielectric layer and a bit line contact layer located on a top surface of the substrate, the bottom dielectric layer has bit line contact openings, the bit line contact openings expose the active areas in the substrate, and the bit line contact layer covers the bottom dielectric layer and fills the bit line contact openings; etching parts of the bit line contact layer, and forming first bit line contact layer with different heights; forming a conductive layer, a top surface of the conductive layer is located at different heights in a direction perpendicular to an extension direction of the word line structures.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.