Memory devices and systems including static and dynamic caches, and related methods
US12131020B2 · kind B2 · utility
0Cited by
10References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 3, 2021 |
| Grant date | Oct 29, 2024 |
| Priority date | — |
| Expiry date | Dec 3, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/7206
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Memory devices are disclosed. A memory device may include dynamic cache, static cache, and a memory controller. The memory controller may be configured to disable the static cache responsive to a number of program/erase (PE) cycles consumed by the static cache being greater than an endurance of the static cache. The memory controller may also be configured to disable the dynamic cache responsive to a number of PE cycles consumed by the dynamic cache being greater than an endurance of the dynamic cache. Associated methods and systems are also disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.