Weak erase pulse

US12131785B2 · kind B2 · utility

Assignee

• Intel NDTM US LLC · US

Inventors

• Chao Zhang · Shanghai, CN
• Krishna K. Parat · Palo Alto, US
• Richard Fastow · Cupertino, US
• Ricardo Basco · Santa Clara, US
• Xin Sun · Shenyang, CN
• Heonwook Kim · San Jose, US
• Zhan Liu · San Jose, US

Key dates

• Filing date: Jun 1, 2022
• Grant date: Oct 29, 2024
• Expiry date: Oct 30, 2042

Classification

• Technology area (CPC G): Physics
• CPC primary: G11C16/349
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

Systems, apparatuses and methods may provide for technology that biases a word line of a block in NAND memory to a first voltage level, biases a source-side select gate and a drain-side select gate of the block to a second voltage level, and issues a discharge erase pulse to bitlines and a source of the block, wherein the discharge erase pulse is issued at a third voltage level, wherein the third voltage level is greater than the first voltage level and the second voltage level, and wherein the third voltage level is less than a fourth voltage level of a standard erase pulse. In one example, the discharge erase pulse injects holes into pillars of the block and bypasses an erase of cells in the pillars of the block.