Fabrication of a vertical fin field effect transistor with reduced dimensional variations
US12136573B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 7, 2023 |
| Grant date | Nov 5, 2024 |
| Priority date | — |
| Expiry date | Sep 7, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/36
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming a fin field effect transistor (finFET) having fin(s) with reduced dimensional variations, including forming a dummy fin trench within a perimeter of a fin pattern region on a substrate, forming a dummy fin fill in the dummy fin trench, forming a plurality of vertical fins within the perimeter of the fin pattern region, including border fins at the perimeter of the fin pattern region and interior fins located within the perimeter and inside the bounds of the border fins, wherein the border fins are formed from the dummy fin fill, and removing the border fins, wherein the border fins are dummy fins and the interior fins are active vertical fins.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.