Patent assignee · US · COMPANY

Adeia Semiconductor Solutions LLC

23Patents
23Active
23Granted
60Portfolio score

Filing activity: Oct 8, 2020 → Mar 21, 2024

Most-cited patents

PatentTitleAreaCited byStatus
US11901438B2 Nanosheet transistor Electricity 1 Active
US11784095B2 Fabrication of a vertical fin field effect transistor with reduced dimensional variations Electricity 1 Active
USRE49794E1 SRAM design to facilitate single fin cut in double sidewall image transfer process General 0 Active
US12369379B2 Nanosheet transistor Electricity 0 Active
US12166110B2 Nanosheet channel-to-source and drain isolation Electricity 0 Active
US12154971B2 Forming nanosheet transistor using sacrificial spacer and inner spacers Electricity 0 Active
US11894462B2 Forming a sacrificial liner for dual channel devices Electricity 0 Active
US12387983B2 Forming self-aligned vias and air-gaps in semiconductor fabrication Electricity 0 Active
US12230544B2 Stacked transistors with different channel widths Electricity 0 Active
US12136573B2 Fabrication of a vertical fin field effect transistor with reduced dimensional variations Electricity 0 Active
US12224203B2 Air gap spacer formation for nano-scale semiconductor devices Electricity 0 Active
US12237368B2 Semiconductor structures including middle-of-line (MOL) capacitance reduction for self-aligned contact in gate stack Electricity 0 Active
US12369367B2 Bulk nanosheet with dielectric isolation Electricity 0 Active
US12218003B2 Selective ILD deposition for fully aligned via with airgap Electricity 0 Active
US12119393B2 Punch through stopper in bulk finFET device Electricity 0 Active
US12183634B2 Selective recessing to form a fully aligned via Electricity 0 Active
US12327730B2 Two-color self-aligned double patterning (SADP) to yield static random access memory (SRAM) and dense logic Electricity 0 Active
US12402403B2 Air gap spacer for metal gates Electricity 0 Active
US11955424B2 Semiconductor device including a porous dielectric layer, and method of forming the semiconductor device Electricity 0 Active
USRE50613E1 FinFET gate cut after dummy gate removal General 0 Active
US12376369B2 FinFET devices Electricity 0 Active
US12322601B2 Alternating hardmasks for tight-pitch line formation Electricity 0 Active
US12237328B2 Minimizing shorting between FinFET epitaxial regions Electricity 0 Active

Source: USPTO / EPO open patent data. Counts and citation impact are objective bibliographic measures.