Foggy-fine drain-side select gate re-program for on-pitch semi-circle drain side select gates
US12142323B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 1, 2022 |
| Grant date | Nov 12, 2024 |
| Priority date | — |
| Expiry date | May 18, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/3418
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory apparatus and method of operation are provided. The apparatus includes drain-side select gate transistors for coupling to a drain-side of memory holes of memory cells and configured to retain a transistor threshold voltage. The memory holes are arranged in rows comprising strings. A control means is configured to program drain-side select gate transistors of the memory holes to an initial transistor threshold voltage using pulses increasing in magnitude by a first transistor step amount during each of a plurality of foggy loops of a foggy program operation. The control means is also configured to program the drain-side select gate transistors of the memory holes to a target transistor threshold voltage using pulses increasing in magnitude by a second transistor step amount during each of a plurality of fine loops of a fine program operation. The first transistor step amount is greater than the second transistor step amount.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.